LTC4222
19
4222fb
APPLICATIONS INFORMATION
Selection of the sense resistor, R
S
, is set by the overcurrent
threshold of 50mV:
 
R
S
=
50mV
I
MAX
=0.01?/DIV>
The MOSFET is sized to handle the power dissipation dur-
ing inrush when output capacitor C
OUT
 is being charged.
A method to determine power dissipation during inrush
is based on the principle that:
   Energy in C
L
 = Energy in Q1
This uses:
 
Energy in C
L
=
1
2
 CV
2
=
1
2
 (0.33mF)(12)
2
or 0.024 joules. Calculate the time it takes to charge up
C
OUT
:
 
t
STARTUP
=
C
L
V
DD
I
INRUSH
I
INRUSH
=
0.33mF  12V
1A
= 4ms
The power dissipated in the MOSFET:
 
P
DISS
=
Energy in C
L
t
STARTUP
=6W
The SOA (safe operating area) curves of candidate MOSFETs
must be evaluated to ensure that the heat capacity of the
package tolerates 6W for 4ms. The SOA curves of the
Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,
satisfying this requirement. Since the FDC653N has less
than 8nF of gate capacitance and we are using a GATE
RC network, the short-circuit stability of the current limit
should be checked and improved by adding a capacitor
from GATE to SOURCE if needed.
The inrush current is set to 1A using C1:
 
C1=
C
L
I
GATE
I
INRUSH
 
C1=
0.33mF  12礎
1A
 or C1=3.9nF
The inrush dI/dt is set to 10A/ms using C
SS
:
 
C
SS
=
I
SS
dl/dt
A
s
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
0.0429
1
R
SENSE
=
10礎  0.0429  1
10000  0.01?/DIV>
= 4.3nF choose 4.7nF
For a start-up time of 4ms with a 2x safety margin we
choose:
 
C
TIMER
=
2  t
STARTUP
12.3ms/礔
+C
SS
2
C
TIMER
=
8ms
12.3ms/礔
+4.7nF  2=0.68礔
Note the minimum value of C
TIMER
 is 10nF .
The UV and OV resistor string values can be solved in the
following method. First pick R3 based on I
STRING
 being
1.235V/R3 at the edge of the OV rising threshold. Then
solve the following equations:
 
R2=
V
OV(OFF)
V
UV(ON)
R3
UV
TH(RISING)
OV
TH(FALLING)
R3
 
R1=
V
UV(ON)
(R3+R2)
UV
TH(RISING)
R3R2
In our case we choose R3 to be 3.4k to give a resistor
string current below 100礎.
Then solving the equations results in R2 = 1.16k and
R1 = 34.6k.
The FB divider is solved by picking R8 and solving for R7,
choosing 3.57k for R8 we get:
 
R7=
V
PWRGD(UP)
R8
FB
TH(RISING)
R8
Resulting in R7 = 30k
A 0.1礔 capacitor, C
F
, is placed on the UV pins to prevent
supply glitches from turning off the GATE via UV or OV .
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